This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. P2002-085117, filed on Mar. 26, 2002; the entire contents of which are incorporated herein by reference.
The present invention relates to a synchronous circuit generating a synchronous clock signal by using multi-phases clock signals.
FIG. 7 is a block diagram of a synchronous circuit of a phase picking system in the related art of the present invention. The conventional synchronous circuit comprises a clock generator 1, a clock selector 2, a phase comparator 3, a phase control circuit 4, a phase information storage circuit 6, a frequency divider 7 and a deserializer 8.
The clock generator 1 includes a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop) and generates a plurality of clock signals differing in phase from each other, so-called multi-phases clock signals, based on a reference signal. The phase comparator 3 detects a phase difference between received serial data and a clock signal selected by the clock selector 2 and then outputs a phase difference signal.
The phase control circuit 4 controls an edge of the clock signal to so as to be positioned in the center of the data based on the phase difference signal detected by the phase comparator 3. The phase information storage circuit 6 stores a clock-selecting signal outputted from the phase control circuit 4, and the clock selector 2 selects a suitable phase clock signal from the multi-phases clock signals according to the clock-selecting signal in the phase information storage circuit 6. The frequency divider 7, which receives the clock signal selected by the clock selector 2, generates a divided clock signal having lower frequency than the selected clock signal and supplies the divided clock signal to the phase control circuit 4, the phase information storage circuit 6 and the deserializer 8. The deserializer 8 converts a received serial data of a high bit rate, which is synchronized with the selected clock signal, into the parallel data of a low bit rate, which is synchronized with the divided clock signal obtained by the frequency divider 7, and outputting the parallel data.
Specifically, in the conventional synchronous circuit, when there is a data transition of the received serial data, a phase difference between the serial data and the selected clock signal is detected, and a phase error of the selected clock signal is adjusted according to this detection result.
A synchronous circuit according to an embodiment of the present invention, comprising:
a clock selector configured to select a suitable phase clock signal from a plurality of clock signals differing in phase from each other in accordance with a clock-selecting signal;
a phase comparator configured to compare a phase of input data with that of the selected clock signal;
a phase control circuit configured to generate a phase control signal in accordance with the comparison result obtained by the phase comparator and to generate the clock-selecting signal in accordance with a offset control signal; and
a frequency offset control circuit configured to generate the offset control signal in accordance with the phase control signal.